As a control apparatus for controlling an electric load such as a motor, there is known an apparatus that performs analog-to-digital (A/D) conversion for an AC current of a motor at the timing when a carrier signal used by a pulse width modulation (PWM) control is at a peak and a valley, and calculates a duty command value on the basis of the converted current data.
In such a control apparatus, in order to prevent a pair of semiconductor devices arranged in the same phase from being simultaneously turned on when generating a PWM signal in response to a duty command value, a delay time called a “dead time” is provided in the PWM signal. In addition, a center timing of an ON period of the PWM signal provided with the dead time is deviated from an A/D conversion timing executed in a peak and a valley of the carrier signal, and a sampling error is included as a noise in the current data subjected to the A/D conversion.
In this regard, JP2007-159185A discusses a technique of matching the A/D conversion timing with the center timing of the ON period of the PWM signal by shifting the A/D conversion timing by a half of a predetermined dead time from the peak or the valley of the carrier signal.